Vertical architectures for field effect transistors may have various advantages, including increased density and performance. However, fabricating such structures with deposition, masking, and etching processes may be challenging, in part because devices made with such processes may exhibit considerable variation in gate length and spacer thickness.
Thus, there is a need for a process for fabricating vertical field effect transistors that is capable of providing good control of device parameters, such as gate length and spacer thickness.